(1) Field of the Invention
The invention relates to a method of metallization in the fabrication of integrated circuits, and more particularly, to a method of tungsten metallization which avoids dimple formation during tungsten etch back resulting in improved step coverage in the manufacture of integrated circuits.
(2) Description of the Prior Art
The conventional tungsten etching back process has an inevitable dimple formation at the center of the tungsten plug hole. The dimple feature will result in bad metal step coverage across the tungsten plug during metal deposition after tungsten etching back. This problem will become progressively worse at higher levels of metallization if the stacked via scheme is implemented.
Referring now to FIG. 1, there is illustrated a conventional tungsten plug process of the prior art. There is shown semiconductor substrate 10 in which have been formed source/drain regions 14. Gate electrode 18 has been formed overlying the gate silicon oxide layer 16. A contact hole has been opened through the insulating layer 20 to the source and drain region 14. The glue layer 22 has been deposited over the surface of the substrate and within the contact hole. A layer of tungsten 24 has been deposited over the surface of the glue layer within the contact hole.
Referring now to FIG. 2, the tungsten is etched back using conventional SF.sub.6 /N.sub.2 plasmas, resulting in recess 25 and dimple 26. This dimple formation will degrade the metal deposition conformity across the tungsten plug. A metal void may occur at metal level 3 or 4 if stacked via and tungsten plug methods are implemented. The dimple may also increase the difficulty of intermetal dielectric planarization.
Workers in the art have tried to avoid the tungsten plug dimple problem by using thick chemical vapor deposited (CVD) tungsten on the order of 8000 Angstroms for to improve tungsten deposition conformity and to alleviate the dimple problem in etching back. However, the dimple problem still occurs because over etching is inevitable.
Others have striven to solve some of these problems. For example, U.S. Pat. No. 5,506,168 (Morita et al) shows various methods of creating a raised portion of a plug. U.S. Pat. No. 5,527,736 (Huang et al) shows a method of forming a dimple free plug process. However, these methods can be further improved.